Add imxrt118x architecture and imxrt1180-evk board configurations - #20114

- Only submit and account for a wrapped second TX segment when scatter/gather descriptors
  are available. Without in-memory TCDs, submitting the second segment overwrites the
  active hardware descriptor and incorrectly advances the serial buffer past unsent data.
- Invalidate DMA RX buffer initially

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

Add imxrt118x memorymaps as hardware/rt118x/imxrt118x_memorymap.h

Assisted-by: Claude Code:claude-opus-4-8
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

Add interrupt numbering for imxrt118x in imxrt118x_irq.h, and support
for more interrupts in imxrt_irq.c and imxrt_clrpend.c.

The interrupt numbers are generated from the Reference Manual by AI

Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

i.MXRT118x have a Cortex-M33, which is ARMv8-M. Add cache line definitions
for this one.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

Port the ccm / clock configuration from iMX93 to iMXRT118x.
Register definitions are generated from RM using AI

Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

…controller

Add a header file defining the imxrt118x GPC registers

Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

Add register definitions for IMXRT118x Analog-Digital top level block.

Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

Support reading the OCOTP via the shadow register on imxrt chips with integrated
ELE. On these chips, writing is done via ELE, this is not yet implemented.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

Add IMXRT AONMIX register addresses and bit definitions in a separate header file
"imxrt118x_blkctrl.h".

The header is generated using AI from imxrt118x reference manual.

Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

The trdc driver has been copied from arm64/imx93, and modified to fit imxrt118x.

The relevant register definitions have been generated by AI from the RM.

Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

iMXRT118x uses the same security element as the imx93. Just add iMXRT specific
register definitions and port over the driver code.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

…form

- Initialize the internal secure element, if configured
- Initialize the TRDC, if configured
- Disable the TCM enabling code when compiling for other than Cortex-M7 chip.
  This needs to be skipped for M33 core on imx118x

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

Add the definitions for the Inter-Peripheral Crossbar Switch for iMXRT118x

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

- Add imxrt118x compatible IOMUX definitions, named as IOMUX_VER3. This is the
same IP as what is used for example for IMX9. Instead of directly copying the support
from imx9, pack the padconfig into the same 32-bit value used for GPIO for easy use.

- Add imxrt118x compatible rgpio driver. This is the same GPIO block as what has been used
in imx9. Instead of directly copying the support from IMX9, add pin muxing directly
into GPIO driver as well, to keep the usage compatible with existing IMXRT boards.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

- Small additions to existing drivers to support more UARTs
- Properly invalidate the cache over DMA RX buffer initially

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

- Move/make sure that ep0buf is in usb dma capable memory. Especially if
  .data/.bss are in TCM, the buffers need to be placed in another section.
  If the section .dmamemory doesn't exist, they will end up in .data like before
- change "#ifdef CONFIG_ARCH_FAMILY_IMXRT117x" into
  "#if defined(CONFIG_ARCH_FAMILY_IMXRT117x) || defined(CONFIG_ARCH_FAMILY_IMXRT118x)"
- In imxrt_epcomplete dtd->buffer0 must NOT be used to compute the data buffer's
  cache-maintenance address range. The hardware advances buffer0 (and its
  "current offset" low-order bits) as the transfer progresses, so by completion
  time it points *past* the start of the buffer (at start + xfer_len), not at
  the buffer itself. Instead, use the original privreq->req.buf when the transfer
  is complete.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

Add a few !defined(CONFIG_ARCH_FAMILY_IMXRT118x) gates similar to 1176 to
buid the common drivers also for 118x variants.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

- Add driver supporting the DMA3 and DMA4 in iMXRT118x chips. The driver is first copied
  from imx93, and then changed just the relevant parts (function names, clocking and
  irq handling) to match the imx118x configuration.
- Add the DMA channel numbering in hardware/rt118x/imxrt118x_dmamux.h from RM
  by claude.

Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

Add a function which can be called from M33 core on imx118x to start
executing on M7 core.

The function:
- Configures the M7 clock root
- Releases M7 from reset
- Asks the secure element to release the M7 (ENABLE_APC)
- Enables the M7 clock

The function is compiled in when a configuration flag
CONFIG_IMXRT_CM7_BOOT=y

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

We must enable the MPU on IMXRT118x to be able to keep writeback dcache on.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

…urations

This adds the initial board configurattions for building NuttX for imxrt1189-evk.

The board boots on Cortex-M33 core, for which there are two m33 targets: nsh-m33 and bl.

- "bl" target does basic initialization of ELE and TRDC and just releases the M7 to run
  at 0x20080000.
- "nsh-m33" target just boots nuttx into nsh shell on m33

- The "nsh" target is for M7 core. It can be flashed at 0x20080000, and
  it boots to nsh shell with a proper bootloader on m33 (the bl target does this).

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

…80-evk

Add the documentation for the new supported board configurations and for the architecture,

Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>